HomeInhenyeriyavol. 1 no. 1 (2000)

Hardware Design of an Arithmetic Co-processor Implementing KOHONEN's Self-Organizing Feature Map Computations

Lyne R. Palomar | Toshio Fukuda | Elmer P. Dadios

Discipline: Engineering



A VHDL model of an arithmetic co-processor was implemented with two Self-Organizing Feature Map (SOFM) arithmetic processes: distance computation and weight update. The co-processor was interfaced with a microprocessor-based or microcontroller-based system. A faster execution of the intensively-used arithmetic processes was achieved due to the inherent parallelism adapted in the co-processor’s design. For a 16-bit signed integer or fixed-point data representation, a tolerance of ±2 for the least significant digit was observed. A complete process of 30 to 34 clock cycle was obtained during a model consisting of 4 computational units.